A high-precision time-to-digital converter using a multi-cycle sub-interpolation method evaluated in a Kintex-7 FPGA

Abstract

In FPGA-based TDC design, the tapped delay line (TDL) method is a classical implementation scheme. However, the inherent delay of TDL can limit the accuracy and resolution of TDC; the inhomogeneity of the delay units and a few ultra-wide delay units can impact the accuracy and induce nonlinearity. In this paper, we propose a multi-cycle sub-interpolation method, which constructs a long TDL and performs multiple repetitive measurements over several cycles after the hit signal arrives. This approach not only effectively enhances the TDC accuracy and reduces differential nonlinearity (DNL), but also eliminates the issue of ultra-wide delay units spanning multiple clock regions in the TDL. We implement a four-cycle sub-interpolation method on an AMD Kintex-7 FPGA, achieving an LSB of 3.11 ps, with a DNL range of (−0.995, 2.757) LSB, an INL range of (−4.315, 14.266) LSB, and a timing precision ranging of (3.6, 4.8) ps at different time intervals.