A 5-GHz Fractional-N Reference-Sampling PLL With Voltage-Averaging Fractional Phase Detector Achieving an Integer-N-Level Phase Noise

Abstract

A fractional phase detector (PD) architecture that can significantly reduce the quantization error of a fractional-N phase-locked loop (PLL) is presented. It achieves instantaneous fractional phase detection by spatial averaging in the voltage domain through an array of reference-sampling PD (RSPD) cells. With this fractional PD, a prototype 5-GHz fractional-N RSPLL is implemented in a 65-nm CMOS process. Measurement results show that the in-band and out-of-band phase noises are reduced by 21 and 33 dB, respectively, leading to a significant reduction of the integrated rms jitter from 6.35 ps to 456 fs, almost the same as that at the integer-N mode (442 fs).