srNAND: A Novel NAND Flash Organization for Enhanced Small Read Throughput in SSDs

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-03-19 DOI:10.1109/LCA.2025.3571321

Jeongho Lee;Sangjun Kim;Jaeyong Lee;Jaeyoung Kang;Sungjin Lee;Nam Sung Kim;Jihong Kim

引用次数: 0

Abstract

Emerging data-intensive applications with frequent small random read operations challenge the throughput capabilities of conventional SSD architectures. Although Compute Express Link enabled SSDs allow for fine-grained data access with reduced latency, their read throughput remains limited by legacy block-oriented designs. To address this, we propose

${\sf srNAND}$

, an advanced NAND flash architecture for CXL SSDs. It uses a two-stage ECC decoding mechanism to reduce read amplification, an optimized read command sequence to boost parallelism, and a request merging module to eliminate redundant operations. Our evaluation shows that

${\sf srSSD}$

can improve read throughput by up to 10.4× compared to conventional CXL SSDs.

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srNAND：一种提高ssd小读吞吐量的新型NAND闪存组织

新兴的数据密集型应用程序具有频繁的小随机读取操作，对传统SSD架构的吞吐量能力提出了挑战。尽管支持Compute Express Link的ssd支持细粒度的数据访问，同时降低了延迟，但它们的读取吞吐量仍然受到传统的面向块设计的限制。为了解决这个问题，我们提出了${\sf srNAND}$，这是一种用于CXL ssd的高级NAND闪存架构。它使用两阶段ECC解码机制来减少读放大，一个优化的读命令序列来提高并行性，以及一个请求合并模块来消除冗余操作。我们的评估表明，与传统的CXL ssd相比，${\sf srSSD}$可以将读取吞吐量提高10.4倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.