Memory Optimized, High Signal Quality Direct Digital Frequency Synthesizer on an FPGA

Abstract

Direct digital frequency synthesis is a method for generating digital samples of periodic analog signals. It has been broadly used for decades in applications such as digital radios and radars. The common approaches utilize read-only memory (ROM) for creating amplitude values, and a lot of research focus has been put into reducing the required ROM size. In this brief, we are presenting a memory optimized Direct Digital Frequency Synthesizer (DDFS) architecture that applies the $3{^{\text {rd}}}$ order Taylor series approximation for amplitude computation. To evaluate the architecture performance, also traditional ROM-based architecture is introduced. Both approaches are implemented using VHDL code on a field programmable gate array (FPGA). The FPGA resource utilization, memory consumption, and signal quality are analyzed and compared with other recently published DDFS approaches. Based on the simulation and implementation results, the proposed new architecture consumes only 270 bits of memory and has the output signal spurious free dynamic range (SFDR) of –103.6 dBc.