A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-13 DOI:10.1109/TVLSI.2025.3557673

Sanjoy Kumar Dey;Arun Kumar Barman;Pawan Sehgal;Mukul Sarkar;Shouribrata Chatterjee

{"title":"A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications","authors":"Sanjoy Kumar Dey;Arun Kumar Barman;Pawan Sehgal;Mukul Sarkar;Shouribrata Chatterjee","doi":"10.1109/TVLSI.2025.3557673","DOIUrl":null,"url":null,"abstract":"A 14-bit, 6.7 MS/s successive-approximation-register (SAR) A/D converter (ADC) is presented with on-chip autocalibration. An all-digital calibration algorithm with only two extra half-unit capacitors in capacitive DAC (CDAC) enables the ADC to correct itself from mismatch errors. We introduce digital heavy on-the-fly autocalibration, with novel reuse mechanism of existing capacitors, which deliver analog-precision error-correction yielding superior integral-nonlinearity (INL) and spurious free dynamic range (SFDR) at lowest area. The design is limited by thermal noise and not by mismatch error. A self-shut mechanism in dynamic comparator saves power consumption. A 0.018 mm<sup>2</sup> test chip in a 65-nm CMOS process consumes <inline-formula> <tex-math>$98~\\mu $ </tex-math></inline-formula>W power. The calibration improves the INL of the ADC from >20 least significant bit (LSB) to <2.9> <tex-math>${}_{W}$ </tex-math></inline-formula> of 5.8 fJ/conv-step and FoM<inline-formula> <tex-math>${}_{S}$ </tex-math></inline-formula> of 175 dB at an area efficiency (AE) of <inline-formula> <tex-math>$7.2~\\mu $ </tex-math></inline-formula>m<sup>2</sup>/code.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 7","pages":"1826-1837"},"PeriodicalIF":2.8000,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11002748/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

A 14-bit, 6.7 MS/s successive-approximation-register (SAR) A/D converter (ADC) is presented with on-chip autocalibration. An all-digital calibration algorithm with only two extra half-unit capacitors in capacitive DAC (CDAC) enables the ADC to correct itself from mismatch errors. We introduce digital heavy on-the-fly autocalibration, with novel reuse mechanism of existing capacitors, which deliver analog-precision error-correction yielding superior integral-nonlinearity (INL) and spurious free dynamic range (SFDR) at lowest area. The design is limited by thermal noise and not by mismatch error. A self-shut mechanism in dynamic comparator saves power consumption. A 0.018 mm² test chip in a 65-nm CMOS process consumes

$98~\mu $

W power. The calibration improves the INL of the ADC from >20 least significant bit (LSB) to <2.9> ${}_{W}$ of 5.8 fJ/conv-step and FoM

${}_{S}$

of 175 dB at an area efficiency (AE) of

$7.2~\mu $

m²/code.

查看原文本刊更多论文

一种14位6.7 MS/s 0.018 mm2 98 μW SAR A/D转换器，用于阵列应用的动态自动校准

提出了一种14位、6.7 MS/s连续逼近寄存器（SAR）的片上自动校准A/D转换器（ADC）。电容式DAC （CDAC）的全数字校准算法只需要两个额外的半单位电容，就可以使ADC从失配误差中自我校正。我们引入了数字重动态自动校准，利用现有电容器的新颖重用机制，提供模拟精度的误差校正，在最低区域产生卓越的积分非线性（INL）和无杂散动态范围（SFDR）。该设计受到热噪声的限制，而不受失配误差的限制。动态比较器采用自闭机构，节省功耗。采用65纳米CMOS工艺的0.018 mm2测试芯片功耗为98~\mu $ W。该校准将ADC的INL从bbb20最低有效位（LSB）提高到${}_{W}$ 5.8 fJ/反步，FoM ${}_{S}$ 175 dB，面积效率（AE）为$7.2~\mu $ m2/码。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.