A 28-nm Cascode Current Mirror-Based Inconsistency-Free Charging-and-Discharging SRAM-CIM Macro for High-Efficient Convolutional Neural Networks

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-04-07 DOI:10.1109/TVLSI.2025.3552641

Chunyu Peng;Jiating Guo;Shengyuan Yan;Yiming Wei;Xiaohang Chen;Wenjuan Lu;Chenghu Dai;Zhiting Lin;Xiulong Wu

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引用次数: 0

Abstract

Computing-in-memory (CIM) is an emerging approach to alleviate the von Neumann bottleneck and enhance energy efficiency and throughput. This brief introduces a 16-Kb static random access memory (SRAM) CIM macro for convolutional neural networks (CNNs), featuring a cascode current mirror-based inconsistency-free computing circuits (CICCs). The bias voltage of CICC is provided by a cascode current mirror (CCM) circuit. The proposed architecture improves the consistency and linearity of bitline (BL) charge and discharge rates in the analog current domain, enhancing computational accuracy. Additionally, the charge and discharge on the BLs represent the positive or negative calculation result, eliminating the need for extra encoding and logic circuits to handle sign bits. The SRAM-CIM macro achieves an energy efficiency of 59.1–134.0 TOPS/W and a throughput of 0.41 TOPS in a 28-nm CMOS technology, and the estimated inference accuracy on MNIST and CIFAR-10 datasets is 96.5% and 91.4%, respectively, with 5-bit input precision and 1-bit weight precision.

查看原文本刊更多论文

基于28纳米Cascode电流镜的高效卷积神经网络无不一致性充放电SRAM-CIM宏

内存计算（CIM）是一种缓解冯诺依曼瓶颈、提高能源效率和吞吐量的新兴方法。本文介绍了一种用于卷积神经网络（cnn）的16kb静态随机存取存储器（SRAM） CIM宏，具有基于级联码电流镜像的无不一致性计算电路（ccic）。ccc的偏置电压由级联电流反射电路提供。该结构提高了位线（BL）充放电速率在模拟电流域中的一致性和线性度，提高了计算精度。此外，BLs上的充放电表示正或负的计算结果，从而无需额外的编码和逻辑电路来处理符号位。在28纳米CMOS技术下，SRAM-CIM宏的能量效率为59.1-134.0 TOPS/W，吞吐量为0.41 TOPS，在MNIST和CIFAR-10数据集上的估计推理精度分别为96.5%和91.4%，输入精度为5位，权重精度为1位。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.