A 3.7-nW 248-ppm/°C Subthreshold Self-Biased CMOS Current Reference

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-18 DOI:10.1109/TVLSI.2025.3546730

Jingjing Liu;Yuxuan Huang;Weijie Ge;Wenji Mo;Yuchen Wang;Feng Yan;Kangkang Sun;Bingjun Xiong;Zhipeng Li;Jian Guan

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引用次数: 0

Abstract

A modified self-biased

$\beta $

-multiplier-based current reference (CR) circuit is proposed for ultralow-power Internet of Things (IoT) application and is realized without any resistors, bipolar junction transistors (BJTs), or operational amplifiers (OPAs). The proposed CR circuit directly generates the reference current from a modified

$\beta $

-multiplier, which is biased by a stacked diode-connected MOS transistor (SDMT)-based compensated through a complementary-to-absolute temperature (CTAT) voltage. The proposed CR is implemented in a standard 0.18-

$\mu $

m CMOS process with an active area of 0.0069 mm² and almost all transistors operate in the subthreshold region. Measurement results show that the temperature coefficient (TC) of the CR is 248 ppm/°C in a temperature range from

$- 40~^{\circ }$

C to

$125~^{\circ }$

C. The proposed CR exhibits a line sensitivity (LS) of 0.33%/V within the supply voltage range of 0.8–1.4 V. The output of the CR at room temperature (

$25~^{\circ }$

C) is 1.84 nA with a power consumption of 3.7 nW.

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一个3.7-nW 248-ppm/°C亚阈值自偏置CMOS电流基准

针对超低功耗物联网（IoT）应用，提出了一种改进的自偏置$\beta $乘法器电流基准（CR）电路，该电路不需要任何电阻器、双极结晶体管（bjt）或运算放大器（opa）。所提出的CR电路直接从改进的$\beta $ -乘法器产生参考电流，该电流由基于堆叠二极管连接的MOS晶体管（SDMT）通过互补绝对温度（CTAT）电压补偿偏置。所提出的CR在标准的0.18- $\mu $ m CMOS工艺中实现，其有源面积为0.0069 mm2，几乎所有晶体管都工作在亚阈值区域。测量结果表明，在$- 40~^{\circ }$ ～ $125~^{\circ }$ C的温度范围内，CR的温度系数（TC）为248 ppm/℃，线灵敏度（LS）为0.33%/V within the supply voltage range of 0.8–1.4 V. The output of the CR at room temperature ( $25~^{\circ }$ C) is 1.84 nA with a power consumption of 3.7 nW.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.