IGZO DRAM in three dimensions

IF 40.9 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

Nature Electronics Pub Date : 2025-06-26 DOI:10.1038/s41928-025-01413-2

Matthew Parker

引用次数: 0

Abstract

The researchers — who are based at Huazhong University of Science and Technology and Peking University — create an 8 × 8 array of stacked DRAM. Each cell has two layers with an IGZO transistor that act as read and write transistors, achieving 3-bit memory storage and retention time of 100 s. By converging the current across multiple DRAM columns, it is also possible to achieve in-memory accumulation, reducing the number of computations that occur outside the memory for tasks such as image recognition. This is demonstrated in a neural network model for handwritten digit recognition that achieves 95% accuracy.

Original reference: Sci. Adv. 11, eadu4323 (2025)

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三维IGZO DRAM

来自华中科技大学和北京大学的研究人员创造了一种8 × 8的堆叠DRAM阵列。每个单元有两层，其中一个IGZO晶体管作为读写晶体管，实现3位内存存储和100秒的保持时间。通过在多个DRAM列之间汇聚电流，还可以实现内存中的积累，从而减少图像识别等任务在内存之外进行的计算次数。这在手写数字识别的神经网络模型中得到了证明，该模型达到了95%的准确率。原始参考文献：Sci。adv11, eadu4323 （2025）

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Nature Electronics Engineering-Electrical and Electronic Engineering

CiteScore

47.50

自引率

2.30%

发文量

159

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