Multiobjective Design and Performance Evaluation of III–V High-k Surrounding Gate Tunnel Field Effect Transistors Using Machine Learning Approaches

Abstract

In this work, utilising the MultiObjective Optimisation (MOO) framework, III–V tunnel field effect transistors with surrounding gate (III–V TFETs [SG]) have been designed to optimise speed, power and variation for improved device logic parameters. III–V TFET are enhanced by combining the advantages of high-k Hafnium dioxide (HfO₂) dielectric and surrounding gate technologies. III–V TFETs (SG) have collaborated with indium arsenide (InAs) and gallium antimonide (GaSb) to offer better electron mobility, which further improves device performance. By augmenting the MOO framework and machine learning (ML) methods, we have performed the optimisation of III–V high-k TFETs with surrounding gate (III–V high-k TFETs [SG]) by efficiently handling the competing targets. Two advanced MOO algorithms—Non-Dominated Sorting (NS) Genetic Algorithm-III (GA-III) and Pareto Active-Learning Algorithm (PA-L)—are examined. Moreover, it has been demonstrated that ML-based MOO can automatically identify the best solutions for III–V high-k TFETs with Surrounding Gate, influencing the development of the next generation of nanoscale transistors.