{"title":"A comprehensive analysis of SNSFET, HS-NSFET and PHS-NSFET: Temperature and channel doping perspective","authors":"M. Balasubrahmanyam, Ekta Goel","doi":"10.1016/j.micrna.2025.208252","DOIUrl":null,"url":null,"abstract":"<div><div>This study examines the impact of temperature and channel doping on the performance of three advanced gate-all-around field effect transistor designs i.e. Stacked nanosheet FET (SNSFET), H-shaped NSFET (HS NSFET), and the Pyramidal H-shaped NSFET (PHS NSFET) using sentaurus TACD tool. Various DC parameters such as drain-induced barrier lowering (DIBL), I<sub>ON</sub>, I<sub>ON</sub>/I<sub>OFF</sub> ratio, subthreshold swing (SS), and threshold voltage (V<sub>th</sub>), and AC/RF parameters such as transconductance (g<sub>m</sub>), gate-gate capacitance (C<sub>gg</sub>), cut-off frequency (f<sub>T</sub>), gain bandwidth product (GBP), and transconductance frequency product (TFP) are evaluated at different temperatures of 250 K, 300 K, 350 K, and 400 K, for different channel doping concentrations of 10<sup>15</sup> cm<sup>−3</sup>, 10<sup>16</sup> cm<sup>−3</sup>, 10<sup>17</sup> cm<sup>−3</sup>, and 10<sup>18</sup> cm<sup>−3</sup>. The PHS NSFET shows, less variation in its DC/Analog parameters with respect to temperature, compared to SNSFET and HS NSFET proving PHS NSFET thermally stable for next generation semiconductor technologies. The PHS NSFET is found to have high noise margin compared to SNSFET and HS NSFET.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"206 ","pages":"Article 208252"},"PeriodicalIF":2.7000,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325001815","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
引用次数: 0
Abstract
This study examines the impact of temperature and channel doping on the performance of three advanced gate-all-around field effect transistor designs i.e. Stacked nanosheet FET (SNSFET), H-shaped NSFET (HS NSFET), and the Pyramidal H-shaped NSFET (PHS NSFET) using sentaurus TACD tool. Various DC parameters such as drain-induced barrier lowering (DIBL), ION, ION/IOFF ratio, subthreshold swing (SS), and threshold voltage (Vth), and AC/RF parameters such as transconductance (gm), gate-gate capacitance (Cgg), cut-off frequency (fT), gain bandwidth product (GBP), and transconductance frequency product (TFP) are evaluated at different temperatures of 250 K, 300 K, 350 K, and 400 K, for different channel doping concentrations of 1015 cm−3, 1016 cm−3, 1017 cm−3, and 1018 cm−3. The PHS NSFET shows, less variation in its DC/Analog parameters with respect to temperature, compared to SNSFET and HS NSFET proving PHS NSFET thermally stable for next generation semiconductor technologies. The PHS NSFET is found to have high noise margin compared to SNSFET and HS NSFET.