Yuzhou Chen;Zhenyu Li;Dongxu Lyu;Yansong Xu;Guanghui He
{"title":"Neural Rendering Acceleration With Deferred Neural Decoding and Voxel-Centric Data Flow","authors":"Yuzhou Chen;Zhenyu Li;Dongxu Lyu;Yansong Xu;Guanghui He","doi":"10.1109/TCAD.2024.3524918","DOIUrl":null,"url":null,"abstract":"Neural radiance field has become a fundamental rendering technique across diverse applications such as augmented/virtual reality and autonomous driving. It achieves exceptional rendering quality and reduces model construction cost mainly by introducing a novel neural representation, instant neural graphics primitives (Instant-NGPs). Despite its superiority, Instant-NGP poses severe problems of intensive computation, memory inefficiency and pipeline inefficiency, owing to numerous neural network queries, irregular memory access and intricate sampling procedure. To address these issues, this article proposes NeRA, an algorithm-architecture co-optimization framework that facilitates the efficient neural rendering of Instant-NGP. For intensive computation, we reconstruct the rendering flow and propose a deferred neural decoding algorithm to aggregate the network queries, which reduces the computational workload by 85.6% and only incurs <0.5%> <tex-math>$\\Delta $ </tex-math></inline-formula> interpolation algorithm is proposed to condense the scattered memory access and improves the equivalent bandwidth of on-chip memory by <inline-formula> <tex-math>$2.38\\times $ </tex-math></inline-formula>. Furthermore, a voxel-centric data flow is proposed to fully reuse the cached data and save 88.7% of the external memory access. For pipeline inefficiency, a highly-pipelined hardware architecture with decoupled spatial skipping and interleaved sampling is constructed to eliminate the bubbles and invalid samples in the pipeline, which boosts the overall throughput by <inline-formula> <tex-math>$2.41\\times $ </tex-math></inline-formula>. Extensively evaluated on representative benchmarks, NeRA attains <inline-formula> <tex-math>$1.2\\sim 2.9\\times $ </tex-math></inline-formula> in rendering throughput, <inline-formula> <tex-math>$1.7\\sim 36.5\\times $ </tex-math></inline-formula> in energy-efficiency and <inline-formula> <tex-math>$3.6\\sim 8.3\\times $ </tex-math></inline-formula> in area-efficiency, compared to the state-of-the-art related architectures.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 7","pages":"2725-2737"},"PeriodicalIF":2.7000,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10819500/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Neural radiance field has become a fundamental rendering technique across diverse applications such as augmented/virtual reality and autonomous driving. It achieves exceptional rendering quality and reduces model construction cost mainly by introducing a novel neural representation, instant neural graphics primitives (Instant-NGPs). Despite its superiority, Instant-NGP poses severe problems of intensive computation, memory inefficiency and pipeline inefficiency, owing to numerous neural network queries, irregular memory access and intricate sampling procedure. To address these issues, this article proposes NeRA, an algorithm-architecture co-optimization framework that facilitates the efficient neural rendering of Instant-NGP. For intensive computation, we reconstruct the rendering flow and propose a deferred neural decoding algorithm to aggregate the network queries, which reduces the computational workload by 85.6% and only incurs <0.5%> $\Delta $ interpolation algorithm is proposed to condense the scattered memory access and improves the equivalent bandwidth of on-chip memory by $2.38\times $ . Furthermore, a voxel-centric data flow is proposed to fully reuse the cached data and save 88.7% of the external memory access. For pipeline inefficiency, a highly-pipelined hardware architecture with decoupled spatial skipping and interleaved sampling is constructed to eliminate the bubbles and invalid samples in the pipeline, which boosts the overall throughput by $2.41\times $ . Extensively evaluated on representative benchmarks, NeRA attains $1.2\sim 2.9\times $ in rendering throughput, $1.7\sim 36.5\times $ in energy-efficiency and $3.6\sim 8.3\times $ in area-efficiency, compared to the state-of-the-art related architectures.
神经辐射场已经成为各种应用的基本渲染技术,如增强/虚拟现实和自动驾驶。它主要通过引入一种新的神经表示,即即时神经图形原语(instant - ngps)来实现卓越的渲染质量并降低模型构建成本。尽管具有优势,但由于神经网络查询次数多、内存访问不规则和采样过程复杂,Instant-NGP存在严重的计算量大、内存效率低和流水线效率低的问题。为了解决这些问题,本文提出了NeRA,这是一个算法架构协同优化框架,促进了Instant-NGP的高效神经渲染。对于密集的计算,我们重构了渲染流,并提出了一种延迟神经解码算法来聚合网络查询,减少了85.6的计算量% and only incurs $\Delta $ interpolation algorithm is proposed to condense the scattered memory access and improves the equivalent bandwidth of on-chip memory by $2.38\times $ . Furthermore, a voxel-centric data flow is proposed to fully reuse the cached data and save 88.7% of the external memory access. For pipeline inefficiency, a highly-pipelined hardware architecture with decoupled spatial skipping and interleaved sampling is constructed to eliminate the bubbles and invalid samples in the pipeline, which boosts the overall throughput by $2.41\times $ . Extensively evaluated on representative benchmarks, NeRA attains $1.2\sim 2.9\times $ in rendering throughput, $1.7\sim 36.5\times $ in energy-efficiency and $3.6\sim 8.3\times $ in area-efficiency, compared to the state-of-the-art related architectures.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.