Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Matteo Perotti;Samuel Riedel;Matheus Cavalcante;Luca Benini
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Abstract

The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficient computer architectures. To mitigate the bottlenecks of typical processor-based architectures on both the instruction and data sides of the memory, we present Spatz, a compact 64 bit floating-point-capable vector processor based on RISC-V’s vector extension Zve64d. Using Spatz as the main Processing Element (PE), we design an open-source dualcore vector processor architecture based on a modular and scalable cluster sharing a Scratchpad Memory (SCM). Unlike typical vector processors, whose Vector Register Files (VRFs) are hundreds of KiB large, we prove that Spatz can achieve peak energy efficiency with a latch-based VRF of only 2 KiB. An implementation of the Spatz-based cluster in GlobalFoundries’ 12LPP process with eight double-precision Floating Point Units (FPUs) achieves an FPU utilization just 3.4% lower than the ideal upper bound on a double-precision, floating-point matrix multiplication. The cluster reaches 7.7 FMA/cycle, corresponding to 15.7 DP-GFLOPS and 95.7 GFLOPSDP/W at 1 GHz and nominal operating conditions (TT, 0.80 V, and 25 °C), with more than 55% of the power spent on the FPUs. Furthermore, the optimally balanced Spatz-based cluster reaches a 95.0% FPU utilization (7.6 FMA/cycle), 15.2 GFLOPSDP, and 99.3 GFLOPSDP/W (61% of the power spent in the FPU) on a 2D workload with $7\times 7$ kernel, resulting in an outstanding area/energy efficiency of 171 GFLOPSDP/W/mm2. At equi-area, the computing cluster built upon compact vector processors reaches a 30% higher energy efficiency than a cluster with the same FPU count built upon scalar cores specialized for stream-based floating-point computation.
聚类紧凑的基于risc - v的向量单元以最大化计算效率
现代应用程序不断增加的计算和存储需求以及技术扩展的放缓对设计和实现高效的计算机体系结构提出了重大挑战。为了缓解典型的基于处理器的架构在内存的指令和数据方面的瓶颈,我们提出了Spatz,一种基于RISC-V的矢量扩展Zve64d的紧凑的64位浮点向量处理器。使用Spatz作为主要处理元素(PE),我们设计了一个基于模块化和可扩展集群的开源双核矢量处理器架构,共享一个Scratchpad Memory (SCM)。不像典型的矢量处理器,其矢量寄存器文件(VRF)有数百KiB大,我们证明了Spatz可以实现峰值能源效率,基于锁存器的VRF只有2 KiB。在GlobalFoundries的12LPP工艺中,使用8个双精度浮点单元(FPU)实现基于spatz的集群,其FPU利用率仅比双精度浮点矩阵乘法的理想上限低3.4%。在1ghz和标准工作条件(TT, 0.80 V, 25℃)下,集群达到7.7 FMA/cycle,对应15.7 DP-GFLOPS和95.7 GFLOPSDP/W,其中55%以上的功率花在fpu上。此外,基于spatz的最佳平衡集群在具有$7\ × 7$内核的2D工作负载上达到95.0%的FPU利用率(7.6 FMA/cycle), 15.2 GFLOPSDP和99.3 GFLOPSDP/W (FPU消耗的61%的功率),从而获得171 GFLOPSDP/W/mm2的出色面积/能量效率。在同等面积下,基于紧凑矢量处理器构建的计算集群比基于专门用于基于流的浮点计算的标量内核构建的具有相同FPU数量的集群的能源效率高30%。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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