Understanding Inductor-Originated Single-Event Frequency Transients in CMOS LC -Tank Oscillators: Causes, Effects, and System Impacts

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Gideon Adom-Bamfi;Qichao Ma;Stefan Biereigel;Paul Leroux;Jeffrey Prinzie
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引用次数: 0

Abstract

Single-event frequency transients (SEFTs) in integrated complementary metal oxide semiconductor (CMOS) LC-tank voltage-controlled oscillator (VCO) and digitally-controlled oscillator (DCO), widely used in frequency synthesizer circuits, have recently been observed and linked to single-event effects (SEEs) in on-chip planar spiral inductors. This work provides an explanation of the underlying causes of these transients, presenting, for the first time, a general model to characterize their behavior and examine their system-level impact. Previously reported experimental observations are validated through heavy-ion microbeam irradiation experiments on two- and four-turn spiral inductor test structures, supported by theoretical analysis and simulations. The study highlights that both the patterned ground shield (PGS) and the inductor geometry significantly influence the polarity and magnitude of SEFT peak deviations. In addition, the results confirm that these deviations are frequency-dependent, with their magnitude increasing at higher operating frequencies. At the system level, SEFTs are demonstrated to induce phase errors in phase-locked loops (PLLs), potentially causing data transmission errors in high-speed communication links. The experimental results are obtained from test circuits fabricated using a 65-nm CMOS process, operating at a nominal frequency of 2.56 GHz with a supply voltage of 1.2 V.
理解CMOS LC -Tank振荡器中电感引起的单事件频率瞬变:原因、影响和系统影响
集成互补金属氧化物半导体(CMOS)中的单事件频率瞬变(SEFTs)广泛应用于频率合成器电路中的LC-tank压控振荡器(VCO)和数字控制振荡器(DCO)最近被观察到并与片上平面螺旋电感中的单事件效应(SEEs)相关联。这项工作提供了这些瞬变的潜在原因的解释,首次提出了一个通用模型来表征它们的行为并检查它们的系统级影响。通过对两转和四转螺旋电感试验结构进行重离子微束辐照实验,验证了先前报道的实验结果,并进行了理论分析和仿真。研究强调,图案接地屏蔽(PGS)和电感的几何形状显着影响SEFT峰值偏差的极性和幅度。此外,结果证实这些偏差是频率相关的,其幅度在较高的工作频率下增加。在系统层面,SEFTs被证明会在锁相环(pll)中引起相位误差,从而可能导致高速通信链路中的数据传输错误。实验结果来自采用65纳米CMOS工艺制作的测试电路,工作在2.56 GHz的标称频率下,电源电压为1.2 V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Nuclear Science
IEEE Transactions on Nuclear Science 工程技术-工程:电子与电气
CiteScore
3.70
自引率
27.80%
发文量
314
审稿时长
6.2 months
期刊介绍: The IEEE Transactions on Nuclear Science is a publication of the IEEE Nuclear and Plasma Sciences Society. It is viewed as the primary source of technical information in many of the areas it covers. As judged by JCR impact factor, TNS consistently ranks in the top five journals in the category of Nuclear Science & Technology. It has one of the higher immediacy indices, indicating that the information it publishes is viewed as timely, and has a relatively long citation half-life, indicating that the published information also is viewed as valuable for a number of years. The IEEE Transactions on Nuclear Science is published bimonthly. Its scope includes all aspects of the theory and application of nuclear science and engineering. It focuses on instrumentation for the detection and measurement of ionizing radiation; particle accelerators and their controls; nuclear medicine and its application; effects of radiation on materials, components, and systems; reactor instrumentation and controls; and measurement of radiation in space.
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