Investigation of SiC MOSFET Structures for Surge Robustness in the Third Quadrant Under Various $V_{\text{GS}}$ Biases

Abstract

In this work, SiC planar-gate MOSFET (PG-MOS), SiC short-channel (0.3$\mathbf {\mu m}$) MOSFET (SCMOS), and SiC JBSFET are tested for the third quadrant I-V temperature characteristics and surge current capability at different gate-source bias voltage. The I-V temperature curves and the TCAD simulation reveal that different device structures exhibit distinct temperature variation trends due to different current conduction paths. The surge test results indicate that SiC PGMOS and SiC SCMOS exhibit bipolar conduction modes at ${\mathit{V}}_{\mathbf{GS}} = 0$ V and ${\mathit{V}}_{\mathbf{GS}} = -10$ V. SiC JBSFET operates in a unipolar conduction mode prior to the surge current density threshold of 998.3 $\mathbf {A}/\mathbf {cm}^{\mathbf {2}}$, after which it transitions to a post-bipolar conduction mode, similar to SiC JBS diode. Finally, the failure mechanism is analyzed. The surge current crowding in the edge termination region is a key factor affecting the surge capability of SiC PGMOS. Reducing channel length leads to premature breakdown of the gate-source dielectric layer in SiC SCMOS at ${\mathit{V}}_{\mathbf{GS}} = 0$ V but enhances the surge ability at ${\mathit{V}}_{\mathbf{GS}} = -10$ V. The thermal stress induced by the surge current in SiC JBSFET causes large-scale damage to the source metal and cells, resulting in a short circuit between the gate, source, and drain.