A V-Band Divide-by-6 Injection-Locked Frequency Divider Using Current-Reused Topology With Second Injection and Harmonic Boosting

IF 3.4 0 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE microwave and wireless technology letters Pub Date : 2025-03-26 DOI:10.1109/LMWT.2025.3549756

Po-Yuan Chen;Hong-Yeh Chang

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Abstract

This letter presents a V-band injection-locked frequency divider (ILFD) with high input sensitivity and wide locking range (LR), implemented in 90-nm CMOS technology. The proposed divide-by-6 ILFD employs a modified current-reused topology with second injection and harmonic boosting to enhance the overall LR while maintaining high sensitivity. This architecture consists of two stages: a front-stage divide-by-2 ILFD, followed by a back-stage divide-by-3 ILFD. At an input power of 0 dBm, the measured maximum LR reaches up to 8.1 GHz, covering frequencies from 54.7 to 62.8 GHz. This design achieves the highest LR

$\times {n}$

and has comparable figure of merits (FoMs) among the reported CMOS microwave and millimeter-wave (mm-wave) ILFDs, when operated at lower input powers. Notably, this proposed ILFD offers a unique combination of features: wide LR with a low dc power consumption of 12.2 mW, competitive input sensitivity, and a high division ratio up to six.

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基于二次注入和谐波升压电流复用拓扑的v波段分频器

本文介绍了一种采用90纳米CMOS技术实现的具有高输入灵敏度和宽锁定范围（LR）的v波段注入锁定分频器（ILFD）。所提出的除以6的ILFD采用改进的电流复用拓扑，具有二次注入和谐波增强，以提高整体LR，同时保持高灵敏度。该体系结构由两个阶段组成：前一级除以2的ILFD，然后是后一级除以3的ILFD。在输入功率为0 dBm时，测量到的最大LR可达8.1 GHz，频率范围为54.7 ~ 62.8 GHz。该设计在较低输入功率下工作时，实现了最高的LR $\times {n}$，并且在已有的CMOS微波和毫米波ilfd中具有可比的优点系数（FoMs）。值得注意的是，该ILFD提供了独特的功能组合：宽LR，直流功耗低至12.2 mW，具有竞争力的输入灵敏度，以及高达6的高分割比。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE microwave and wireless technology letters

CiteScore

6.00

自引率

0.00%

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