A 66–160 GHz Broadband Frequency Multiplier Chain (×6) With High Harmonic Suppression

0 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE microwave and wireless technology letters Pub Date : 2025-04-09 DOI:10.1109/LMWT.2025.3556003

Zi'ang Xu;Zihan Zhang;Junjie Zhang;Xiaoyu Zhang;Guangbo Wang;Jian Guo

{"title":"A 66–160 GHz Broadband Frequency Multiplier Chain (×6) With High Harmonic Suppression","authors":"Zi'ang Xu;Zihan Zhang;Junjie Zhang;Xiaoyu Zhang;Guangbo Wang;Jian Guo","doi":"10.1109/LMWT.2025.3556003","DOIUrl":null,"url":null,"abstract":"This letter presents a 66–160 GHz <inline-formula> <tex-math>$\\times 6$ </tex-math></inline-formula> frequency multiplier chain (FMC) in 0.1-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m pHEMT technology with good harmonic suppression performance. The FMC chip integrates four cascaded stages, including a driver amplifier (DA) with a semi-lumped low-pass filter (SLLPF), a double-balanced tripler with a semi-lumped high-pass filter (SLHPF), a balanced DA, and a double-balanced doubler which are designed rigorously for specific harmonic suppression. Balanced configurations join with semi-lumped filters and wideband passive multipliers to achieve broad bandwidth (BW), power flatness, and excellent harmonic suppression. The measured 3-dB BW of the FMC is 66–160 GHz (relative BW of 83.2%), and the measured peak output power is 7 dBm. The harmonic suppression reaches over 25 dBc within 87–160 GHz (relative BW of 59.1%). To the best of our knowledge, the proposed FMC exhibits the widest relative BW, high harmonic suppression, and comparable output power.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 6","pages":"742-745"},"PeriodicalIF":0.0000,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10959337/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

This letter presents a 66–160 GHz

$\times 6$

frequency multiplier chain (FMC) in 0.1-

$\mu $

m pHEMT technology with good harmonic suppression performance. The FMC chip integrates four cascaded stages, including a driver amplifier (DA) with a semi-lumped low-pass filter (SLLPF), a double-balanced tripler with a semi-lumped high-pass filter (SLHPF), a balanced DA, and a double-balanced doubler which are designed rigorously for specific harmonic suppression. Balanced configurations join with semi-lumped filters and wideband passive multipliers to achieve broad bandwidth (BW), power flatness, and excellent harmonic suppression. The measured 3-dB BW of the FMC is 66–160 GHz (relative BW of 83.2%), and the measured peak output power is 7 dBm. The harmonic suppression reaches over 25 dBc within 87–160 GHz (relative BW of 59.1%). To the best of our knowledge, the proposed FMC exhibits the widest relative BW, high harmonic suppression, and comparable output power.

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高谐波抑制的66 - 160ghz宽带倍频链(×6

本文介绍了一种采用0.1- $\mu $ m pHEMT技术的66-160 GHz $\times 6$倍频链（FMC），具有良好的谐波抑制性能。FMC芯片集成了四个级联级，包括带半集总低通滤波器（SLLPF）的驱动放大器（DA），带半集总高通滤波器（SLHPF）的双平衡三频器，平衡DA和双平衡倍频器，这些都是为特定谐波抑制而严格设计的。平衡配置与半集总滤波器和宽带无源乘法器相结合，可实现宽带（BW）、功率平坦性和出色的谐波抑制。FMC的实测3db BW为66 ~ 160 GHz（相对BW为83.2%），实测峰值输出功率为7 dBm。在87 ~ 160 GHz范围内谐波抑制达到25 dBc以上（相对BW为59.1%）。据我们所知，所提出的FMC具有最宽的相对BW，高谐波抑制和相当的输出功率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE microwave and wireless technology letters

CiteScore

6.00

自引率

0.00%

发文量