An Asymmetric Cascode Doherty Power Amplifier With a Transformer-Based Combiner in 65-nm CMOS

Abstract

In this study, we present a high-power back-off (PBO) efficiency asymmetric Doherty power amplifier (Doherty PA), featuring compact transformer-based input/output matching networks. The series output combiner, meticulously designed for asymmetric power ratio synthesis, integrates impedance inverters into the power combiner. This design significantly boosts power additional efficiency within a 9-dB PBO range. The integration of a quarter-wavelength phase compensation circuit and a quadrature power divider, both designed based on transformer structure, effectively minimizes the core chip area. Furthermore, the incorporation of neutralizing capacitor technology within the cascode structure has significantly enhanced gain and stability. The designed Doherty PA is manufactured by 65 nm CMOS technology, achieving 23.2 dBm saturated output power (P_sat) with 28.2% peak power added efficiency (PAE), and 22.4 dBm 1-dB output compression point (OP_1dB) at 38 GHz. The measured PAE at 9-dB PBO efficiency is 16.1%. These figures result in an efficiency enhancement ratio of 1.78 when compared to an ideal class-B PA.