Enhancing VLSI Design Efficiency With ML-Based C-ANN: Performance Optimization of Gate-Stacked Ferroelectric FE-MOSFETs for High-Speed and RF Applications

Abstract

This study presents an innovative approach leveraging TCAD simulations and a Convolutional Artificial Neural Network (C-ANN) to address challenges in VLSI design. A statistical sample of 4000 distinct values was simulated to predict drain current (I_ds), achieving a dramatic reduction in runtime from 46 to 48 days (conventional TCAD) to just 100–120 s using the proposed ML-based C-ANN. The proposed gate-stacking SiO₂ + HfO₂ FE-MOSFET device demonstrates significant advancements, including reductions in short-channel effects (SCEs), subthreshold swing (SS) by 3.12%–4.04%, and drain-induced barrier lowering (DIBL) by 10.19%. Enhanced performance metrics include 52.95% higher I_ON, 90% reduced gate leakage, and improved transconductance g_m, transconductance generation function (TGF), early voltage (V_EA), and intrinsic gain (A_v) by 26.18%, 27.12%, 29.35%, and 101.24%, respectively. RF parameters such as gate capacitance (C_gg), unity gain frequency (f_t), and gain frequency product (GFP) improved by 34.53%, 48.74%, and 21.18%, making this device ideal for high-speed switching and RF applications, promoting efficiency in low-power VLSI designs.