A robust internal reference voltage generation circuit with self-adaptive calibration scheme for receiver in NV-DDR interface

Abstract

This paper models and analyzes the impacts of impedance mismatch and synchronous switch noise (SSN) on data IO signals in NV-DDR interface. Based on the model, a robust internal reference voltage calibration scheme is proposed. This scheme utilizes a low-pass filter to extract the mid level of data eye diagram from the clock pattern data. According to the above level, a self-adaptive calibration loop based on successive approximation search (SAR) algorithm is adopted to quickly generate the internal reference voltage, thus ensuring the reliability of internal reference voltage. The proposed internal reference voltage generation circuit can reduce the interference of impedance mismatch and SSN, and adaptively generate the internal reference voltage in different interface modes. The test chip is fabricated in 180 nm CMOS process and the area occupies 0.0418 mm${}^2$. The measurement results indicate that the internal reference voltage calibration error is within $0.5\text{\%}\cdot VccQ$ under diverse IO signals ranging from 800 MT/s to 2400 MT/s.