Hao Xu , Congyang Sun , Shuai Liu , Guoyu Li , Yechen Tian , Na Yan
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引用次数: 0
Abstract
This work presents a noise-shaping successive-approximation-register (NS-SAR) ADC employing an open-loop Gm-R amplifier. Within the adopted cascaded integrator feed-forward (EF-CIFF) architecture with sampling kT/C noise cancellation, higher speed operation is enabled by the Gm-R amplifier as it simplifies timing control and does not require gain calibration. The quantizer uses 8-bit quantization depth, which is the theoretical optimum quantitatively estimated for the targeted 80 dB signal-to-noise-distortion ratio (SNDR). Fabricated in a 28 nm CMOS process, the prototype NS-SAR ADC operating at 50 MS/s sampling rate achieves 80.6 dB SNDR over a 2 MHz bandwidth with an oversampling ratio (OSR) of 12.5. It occupies 0.026 mm with a total power consumption of 1.275 mW at 1 V supply, resulting in a Schreier figure-of-merits (FoMs) of 172.6 dB.
期刊介绍:
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