Development and comparative analysis of a GAA nanosheet FET across diverse space charge region materials for nanoscale applications

Abstract

Gate-All-Around (GAA) FETs currently dominate the industry due to their primary benefit of reduced overall FET size and enhanced gate electrostatic integrity over the channel from all directions. This study presents a comparative analysis of 10 nm FinFET and nanosheet FET (NS-FET) architectures designed using GAA and fully depleted Silicon-On-Insulator (FD-SOI) technologies. The NS-FETs feature dual-channel structures with uniform doping profiles and various spacer region configurations, including single-K materials (Air, SiO₂) and dual-K combinations (HfO₂+SiO₂, Nitride + HfO₂). A comprehensive evaluation of key performance parameters, including transfer characteristics, threshold voltage, switching ratio, Drain-Induced Barrier Lowering (DIBL), and subthreshold swing (SS), was conducted. Results indicate that NS-FETs demonstrate significant reduction of SCEs compared to FinFETs, with DIBL reductions of 65.34 %, 59.37 %, 81.43 %, and 83.19 %, and SS improvements of 5.28 %, 0.92 %, 0.02 %, and 2.68 % for SiO₂, HfO₂+SiO₂, Nitride + HfO₂, and Air spacers, respectively. Notably, single-K spacers yielded higher I_ON/I_OFF ratios. These findings confirm that strategic spacer material engineering in NS-FETs effectively minimizes leakage currents, thereby enhancing device performance for ultra-scaled, low-power applications.