A Temperature Noise Correction Method for CMOS Spatial Camera Using LSTM With Attention Mechanism

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Long Cheng, Xueying Wang, Jing Xu
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引用次数: 0

Abstract

This study presents an innovative temperature-induced random noise correction method for complementary metal oxide semiconductor (CMOS) spatial cameras using an attention mechanism-enhanced long short-term memory (LSTM) model. The model, specifically designed to address pixel drift and random noise issues in CMOS space cameras due to temperature variations, incorporates a multilayer LSTM network with an attention mechanism. This study comprehensively examines the temperature-induced variations in noise characteristics of CMOS cameras across diverse thermal conditions, encompassing in-depth analyses of both dark-field and light-field scenarios. Through detailed pixel-level analysis, the study quantifies the influence of temperature on pixel values and critical performance parameters such as internal nonuniformity within the camera. The experimental results show that under the dark field condition, the fitting variance between the predicted value and the measured value ranges from 0.29585 to 5.798307. After correction in light field conditions, the average variance of images decreases to 0.29, the mean signal-to-noise ratio (SNR) increases to 80, and the photo response nonuniformity (PRNU) mean drops to 0.0161%. Compared to precorrection levels, these key metrics show significant improvements, with an average 83.57-fold reduction, 1.89-fold increase, and 84.98-fold decrease, respectively. These results confirm the effectiveness of the deep learning method in correcting temperature-induced noise, highlighting the potential for practical engineering applications.

基于LSTM的CMOS空间相机温度噪声校正方法
本研究提出一种基于注意机制增强长短期记忆(LSTM)模型的温度诱导随机噪声校正方法,用于互补金属氧化物半导体(CMOS)空间相机。该模型专门设计用于解决CMOS空间相机中由于温度变化引起的像素漂移和随机噪声问题,并结合了具有注意机制的多层LSTM网络。本研究全面考察了不同热条件下CMOS相机的温度引起的噪声特性变化,包括对暗场和光场场景的深入分析。通过详细的像素级分析,该研究量化了温度对像素值和相机内部不均匀性等关键性能参数的影响。实验结果表明,在暗场条件下,预测值与实测值的拟合方差在0.29585 ~ 5.798307之间。在光场条件下进行校正后,图像的平均方差减小到0.29,平均信噪比(SNR)增加到80,光响应不均匀度(PRNU)平均值下降到0.0161%。与校正前的水平相比,这些关键指标显示出显著改善,平均分别减少83.57倍、增加1.89倍和减少84.98倍。这些结果证实了深度学习方法在纠正温度引起的噪声方面的有效性,突出了实际工程应用的潜力。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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