A cross-voltage-domain sub-sampling phase-locked loop operating from 6.0 GHz to 8.8 GHz

Abstract

This paper presents a cross-voltage-domain sub-sampling phase-locked loop (SSPLL) operating from 6.0 GHz to 8.8 GHz, designed for compatibility with both millimeter-wave (mmWave) and C-band transceivers. Several circuit-level optimizations are applied to enhance performance and efficiency. A dual-voltage-domain architecture is adopted: digital modules operate at a lower voltage (1.2 V) for high speed and reduced power, while analog and RF modules utilize a higher voltage domain (2.5 V) to improve drive strength and noise performance. The level shifter bridges the two voltage domains, and for the first time, a comprehensive analysis of its phase noise performance is presented, providing key insights to prevent SSPLL phase noise degradation. An input divide-by-2 enhances output frequency resolution. A class-C voltage-controlled oscillator (VCO) is adopted to reduce power consumption. The PLL is implemented in a 65 nm CMOS process, occupying a core area of 0.346 mm². The VCO covers a frequency range of 5.98–8.83 GHz. This PLL achieves a root-mean-square (rms) jitter of 500 fs integrated from 10 kHz to 100 MHz with a typical power consumption of 43.6 mW. A reference spur of −55.42 dBc is measured with the PLL operating at 7.8 GHz.