Random Telegraph Noise Due to Dielectric-Semiconductor Interface Traps in MOS Transistors

Abstract

Random telegraph noise (RTN), primarily a gate dielectric-semiconductor interfacial phenomenon in field-effect transistors, is an important parameter of interest for downscaled devices. The existing methods proposed so far do not predict RTN and are fundamentally focused on tracing RTN signals from raw experimental data. Commonly used modern technology computer-aided design (TCAD) tools are equipped with physics-based models to analyze overall noise response in metal-oxide–semiconductor (MOS) devices; however, they lack integrated models, which can predict and plot RTN. This article presents an algorithm for generating RTN characteristics (RTN current versus time) for MOS devices using extracted parameters from noise spectral density (NSD) characteristics. The model is developed, considering tunnel field-effect transistors (TFETs) as primary devices of interest, and later validating for other MOS devices. The model utilizes the properties of interarrival times in a Poisson process along with NSD roll-off at low frequency to calculate the capture and emission times of single interface traps (SITs). The generic nature of the algorithm facilitates its applicability to any MOS based transistors as well and allows integration with the existing TCAD tools. This report also outlines a strategy for developing a random number generator (RNG) from the RTN signal based on the proposed model. The code for generating RTN is openly accessible for use.