An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu
{"title":"An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors","authors":"Qiang Zhao ,&nbsp;Shiqi Dang ,&nbsp;Zhendong Niu ,&nbsp;Bin Qiang ,&nbsp;Chunhui Fan ,&nbsp;Zhigang Li ,&nbsp;Licai Hao ,&nbsp;Chunyu Peng ,&nbsp;Zhiting Lin ,&nbsp;Xiulong Wu","doi":"10.1016/j.mejo.2025.106720","DOIUrl":null,"url":null,"abstract":"<div><div>The use of correlated multiple sampling(CMS) in CMOS image sensor(CIS) can significantly reduce the noise in readout circuits, but employing CMS leads to an increase in the conversion time and power consumption of ADC. This paper presents an interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors. This ADC first uses a 6-bit SAR ADC to perform coarse conversion in order to choose a small-range interval, and then permits the 6-bit fine conversion to be performed only in this interval. In addition, to further reduce power consumption, prejudgment logic is used to eliminate the coarse conversion process by taking advantage of the nature of the similarity of neighboring pixel values in CIS and the structure of SAR ADC that are shared by two columns. The proposed ADC is fabricated using a 130 nm CIS process. The simulation results show that the ADC has a differential nonlinearity (DNL) of -0.75/+1 LSB, an integral nonlinearity (INL) of -1.2/+0.5 LSB, and an input referred noise of 122.5 <span><math><mi>μ</mi></math></span>Vrms , achieving a conversion time of <span><math><mrow><mn>4</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in bright condition, <span><math><mrow><mn>6</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in dark conditions, and the up to 20.3 % reduction in column power consumption relative to traditional CMS ADC without prejudgement logic.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106720"},"PeriodicalIF":1.9000,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001699","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

The use of correlated multiple sampling(CMS) in CMOS image sensor(CIS) can significantly reduce the noise in readout circuits, but employing CMS leads to an increase in the conversion time and power consumption of ADC. This paper presents an interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors. This ADC first uses a 6-bit SAR ADC to perform coarse conversion in order to choose a small-range interval, and then permits the 6-bit fine conversion to be performed only in this interval. In addition, to further reduce power consumption, prejudgment logic is used to eliminate the coarse conversion process by taking advantage of the nature of the similarity of neighboring pixel values in CIS and the structure of SAR ADC that are shared by two columns. The proposed ADC is fabricated using a 130 nm CIS process. The simulation results show that the ADC has a differential nonlinearity (DNL) of -0.75/+1 LSB, an integral nonlinearity (INL) of -1.2/+0.5 LSB, and an input referred noise of 122.5 μVrms , achieving a conversion time of 4.1μs in bright condition, 6.5μs in dark conditions, and the up to 20.3 % reduction in column power consumption relative to traditional CMS ADC without prejudgement logic.
用于低噪声CMOS图像传感器的带预判逻辑的间隔自适应相关多采样ADC
在CMOS图像传感器(CIS)中使用相关多重采样(CMS)可以显著降低读出电路中的噪声,但使用CMS会导致ADC转换时间和功耗的增加。针对低噪声CMOS图像传感器,提出了一种具有预判逻辑的间隔自适应相关多采样ADC。该ADC首先使用6位SAR ADC进行粗转换,以便选择一个小范围的区间,然后只允许在这个区间内进行6位精细转换。此外,为了进一步降低功耗,利用CIS中相邻像素值相似的特性和两列共享的SAR ADC结构,采用预判逻辑消除粗转换过程。所提出的ADC采用130 nm CIS工艺制造。仿真结果表明,该ADC的微分非线性(DNL)为-0.75/+1 LSB,积分非线性(INL)为-1.2/+0.5 LSB,输入参考噪声为122.5 μVrms,在明亮条件下转换时间为4.1μs,在黑暗条件下转换时间为6.5μs,在无预判逻辑的情况下,与传统CMS ADC相比,柱功耗降低20.3%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信