Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu
{"title":"An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors","authors":"Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu","doi":"10.1016/j.mejo.2025.106720","DOIUrl":null,"url":null,"abstract":"<div><div>The use of correlated multiple sampling(CMS) in CMOS image sensor(CIS) can significantly reduce the noise in readout circuits, but employing CMS leads to an increase in the conversion time and power consumption of ADC. This paper presents an interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors. This ADC first uses a 6-bit SAR ADC to perform coarse conversion in order to choose a small-range interval, and then permits the 6-bit fine conversion to be performed only in this interval. In addition, to further reduce power consumption, prejudgment logic is used to eliminate the coarse conversion process by taking advantage of the nature of the similarity of neighboring pixel values in CIS and the structure of SAR ADC that are shared by two columns. The proposed ADC is fabricated using a 130 nm CIS process. The simulation results show that the ADC has a differential nonlinearity (DNL) of -0.75/+1 LSB, an integral nonlinearity (INL) of -1.2/+0.5 LSB, and an input referred noise of 122.5 <span><math><mi>μ</mi></math></span>Vrms , achieving a conversion time of <span><math><mrow><mn>4</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in bright condition, <span><math><mrow><mn>6</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in dark conditions, and the up to 20.3 % reduction in column power consumption relative to traditional CMS ADC without prejudgement logic.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106720"},"PeriodicalIF":1.9000,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001699","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The use of correlated multiple sampling(CMS) in CMOS image sensor(CIS) can significantly reduce the noise in readout circuits, but employing CMS leads to an increase in the conversion time and power consumption of ADC. This paper presents an interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors. This ADC first uses a 6-bit SAR ADC to perform coarse conversion in order to choose a small-range interval, and then permits the 6-bit fine conversion to be performed only in this interval. In addition, to further reduce power consumption, prejudgment logic is used to eliminate the coarse conversion process by taking advantage of the nature of the similarity of neighboring pixel values in CIS and the structure of SAR ADC that are shared by two columns. The proposed ADC is fabricated using a 130 nm CIS process. The simulation results show that the ADC has a differential nonlinearity (DNL) of -0.75/+1 LSB, an integral nonlinearity (INL) of -1.2/+0.5 LSB, and an input referred noise of 122.5 Vrms , achieving a conversion time of in bright condition, in dark conditions, and the up to 20.3 % reduction in column power consumption relative to traditional CMS ADC without prejudgement logic.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.