Segin: Synergistically Enabling Fine-Grained Multi-Tenant and Resource Optimized SpMV

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-04-17 DOI:10.1109/LCA.2025.3562120

Helya Hosseini;Ubaid Bakhtiar;Donghyeon Joo;Bahar Asgari

引用次数: 0

Abstract

Sparse matrix-vector multiplication (SpMV) is a critical operation across numerous application domains. As a memory-bound kernel, SpMV does not require a complex compute engine but still needs efficient use of available compute units to achieve peak performance efficiently. However, sparsity causes resource underutilization. To efficiently run SpMV, we propose Segin that leverages a novel fine-grained multi-tenancy, allowing multiple SpMV operations to be executed simultaneously on a single hardware with minimal modifications, which in turn improves throughput. To achieve this, Segin employs hierarchical bitmaps, hence a lightweight logical circuit, to quickly and efficiently identify optimal pairs of sparse matrices to overlap. Our evaluations demonstrate that Segin can improve throughput by 1.92×, while enhancing resource utilization.

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Segin：协同启用细粒度多租户和资源优化SpMV

稀疏矩阵向量乘法（SpMV）是一种跨多个应用领域的关键运算。作为一个内存受限的内核，SpMV不需要复杂的计算引擎，但仍然需要有效地利用可用的计算单元来有效地实现峰值性能。然而，稀疏性导致资源利用不足。为了有效地运行SpMV，我们提出了Segin，它利用了一种新颖的细粒度多租户，允许在单个硬件上同时执行多个SpMV操作，只需进行最小的修改，从而提高了吞吐量。为了实现这一点，Segin采用了分层位图，因此是一种轻量级的逻辑电路，可以快速有效地识别要重叠的稀疏矩阵的最佳对。我们的评估表明，Segin可以将吞吐量提高1.92倍，同时提高资源利用率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.