PFV2: Packet fragmentation with variable size and vigorous mapping in time-sensitive networking

IF 3.7 2区 计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Wenyan Yan , Bin Fu , Dongsheng Wei , Renfa Li , Yixue Lei , Yuhang Jia , Guoqi Xie
{"title":"PFV2: Packet fragmentation with variable size and vigorous mapping in time-sensitive networking","authors":"Wenyan Yan ,&nbsp;Bin Fu ,&nbsp;Dongsheng Wei ,&nbsp;Renfa Li ,&nbsp;Yixue Lei ,&nbsp;Yuhang Jia ,&nbsp;Guoqi Xie","doi":"10.1016/j.sysarc.2025.103457","DOIUrl":null,"url":null,"abstract":"<div><div>With the rapid advancement of intelligent automobiles, the ever-growing communication data put forward high bandwidth and low latency requirements. To meet these requirements, automotive Original Equipment Manufacturers (OEMs) widely adopt domain-centralized Electrical/Electronic (E/E) architecture. In this architecture, Time-Sensitive Networking (TSN) is expected to serve as the backbone network because of its high bandwidth and deterministic communication. TSN uses the Gate Control List (GCL) to divide its time length into multiple time slots, and the time intervals of these time slots are non-uniform (equal or unequal). Different flows have varying requirements for time slot sizes. To enhance the acceptance ratio of Time-Triggered (TT) flows through GCL time slot allocation, packet fragmentation (i.e., flow fragmentation) is introduced into TSN in the recent study. The state-of-the-art packet fragmentation solution divides one un-schedulable TT flow into multiple equal-sized packets (i.e., equal-sized time slots). In other words, these fixed-size packets are difficult to be mapped into the time slots with different sizes.</div><div>This study develops a Packet Fragmentation with Variable-size and Vigorous-mapping (PFV2) technique based on the following three innovations: (1) we implement variable-size packet fragmentation, which iteratively divides the un-schedulable TT flow into smaller packets and then dynamically reschedules these packets; (2) we implement the vigorous mapping solution from packets to time slots by deeply searching for available time slots within the flow’s deadline; and (3) we verify PFV2 based on the LS1028A with Cortex-A72 (i.e., the NXP automotive-grade development board). PFV2 improves the acceptance ratio by up to 20.18% and bandwidth utilization by up to 7.024% compared with the state-of-the-art solution. The theoretical and practical co-verification experiments demonstrate that the PFV2 can effectively improve the flow acceptance ratio and outperform the state-of-the-art solution.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"166 ","pages":"Article 103457"},"PeriodicalIF":3.7000,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Systems Architecture","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1383762125001298","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

With the rapid advancement of intelligent automobiles, the ever-growing communication data put forward high bandwidth and low latency requirements. To meet these requirements, automotive Original Equipment Manufacturers (OEMs) widely adopt domain-centralized Electrical/Electronic (E/E) architecture. In this architecture, Time-Sensitive Networking (TSN) is expected to serve as the backbone network because of its high bandwidth and deterministic communication. TSN uses the Gate Control List (GCL) to divide its time length into multiple time slots, and the time intervals of these time slots are non-uniform (equal or unequal). Different flows have varying requirements for time slot sizes. To enhance the acceptance ratio of Time-Triggered (TT) flows through GCL time slot allocation, packet fragmentation (i.e., flow fragmentation) is introduced into TSN in the recent study. The state-of-the-art packet fragmentation solution divides one un-schedulable TT flow into multiple equal-sized packets (i.e., equal-sized time slots). In other words, these fixed-size packets are difficult to be mapped into the time slots with different sizes.
This study develops a Packet Fragmentation with Variable-size and Vigorous-mapping (PFV2) technique based on the following three innovations: (1) we implement variable-size packet fragmentation, which iteratively divides the un-schedulable TT flow into smaller packets and then dynamically reschedules these packets; (2) we implement the vigorous mapping solution from packets to time slots by deeply searching for available time slots within the flow’s deadline; and (3) we verify PFV2 based on the LS1028A with Cortex-A72 (i.e., the NXP automotive-grade development board). PFV2 improves the acceptance ratio by up to 20.18% and bandwidth utilization by up to 7.024% compared with the state-of-the-art solution. The theoretical and practical co-verification experiments demonstrate that the PFV2 can effectively improve the flow acceptance ratio and outperform the state-of-the-art solution.
PFV2:时间敏感网络中可变大小和动态映射的数据包碎片
随着智能汽车的快速发展,不断增长的通信数据提出了高带宽、低时延的要求。为了满足这些需求,汽车原始设备制造商(oem)广泛采用领域集中式电气/电子(E/E)架构。在该体系结构中,时间敏感网络(TSN)由于其高带宽和确定性通信而被期望作为骨干网。TSN使用Gate Control List (GCL)将其时间长度划分为多个时隙,这些时隙的时间间隔是不均匀的(相等或不相等)。不同的流对时隙大小有不同的要求。为了通过GCL时隙分配提高时间触发(time - triggered, TT)流的接受率,最近的研究在TSN中引入了数据包分片(即流分片)。最先进的数据包碎片解决方案将一个不可调度的TT流分成多个大小相等的数据包(即,大小相等的时隙)。换句话说,这些固定大小的数据包很难映射到不同大小的时隙中。本文基于以下三点创新,开发了一种可变大小和强映射的数据包碎片(PFV2)技术:(1)实现了可变大小的数据包碎片,它迭代地将不可调度的TT流划分为更小的数据包,然后动态地重新调度这些数据包;(2)通过深度搜索流截止时间内的可用时隙,实现数据包到时隙的动态映射;(3)基于LS1028A和Cortex-A72(即NXP汽车级开发板)验证PFV2。与最先进的解决方案相比,PFV2的接收率提高了20.18%,带宽利用率提高了7.024%。理论和实际联合验证实验表明,PFV2能有效提高流量接受比,优于现有方案。
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来源期刊
Journal of Systems Architecture
Journal of Systems Architecture 工程技术-计算机:硬件
CiteScore
8.70
自引率
15.60%
发文量
226
审稿时长
46 days
期刊介绍: The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software. Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.
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