Efficient, automated escape routing for high-density pad grids: deepest-exit-first algorithm for layer and wire count optimization.

Abstract

Objective.The burgeoning demand for higher channel count neural interfaces has led to the incorporation of large connectors for connecting electrode channels to recording systems or on-site wireless electronics. However, as these devices are size-constrained for implantation, driving up pad count increases grid density, pushing metal feature sizes to their fabrication limits. Thin-film substrates offer a viable solution, as established microfabrication techniques enhance capabilities over standard electrode manufacturing. Yet, patterning thin-films (TF) still has limitations, requiring multiple layers to wire out the dense grids. This creates a trade-off: more channels require larger connectors and more routing layers, but this reduces flexibility and can make the devices too large for implantation.Approach.In this work we propose an algorithm to efficiently route dense pad grids in the worst scenario case, where traces cannot fit between adjacent pads. We show that the proposed method can route the theoretical maximum number of traces for sufficiently large grids, showing promise for application in very large channel count device designs.Main results.We demonstrate its application on a 1024 channel electrode connected to a dense, flip-chip bonded, wireless recording, application-specific integrated circuit. Comparing the algorithm to standard methods, we achieved improved efficiency in terms of routable traces, number of layers and footprint area. As channel counts increase in TF neural interfaces, escape routing will become more critical. Significance.This algorithm addresses the challenge of mismatched pad density and metal feature size capabilities and automates the design process to ease and accelerate design iteration.