A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2–T Variable Fractional-Spaced FFE in 28-nm CMOS
IF 5.2 1区 工程技术Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
{"title":"A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2–T Variable Fractional-Spaced FFE in 28-nm CMOS","authors":"Ka’Nan Wang;Renjie Tang;Shuyi Xiang;Yukun He;Yunxiang He;Xiaoyan Gui","doi":"10.1109/TCSI.2025.3558331","DOIUrl":null,"url":null,"abstract":"This study presents a 112-Gb/s four-level pulse-amplitude modulation transmitter implemented in a 28-nm CMOS process. An innovative quasi-voltage-mode driver is proposed, which demonstrates similar bandwidth compared to the current-mode logic driver with an approximately 30% power reduction and provides flexible linearity fine-tuning. The TX architectures with and without the pre-driver stage are optimized to exploit the bandwidth limit further. A three-tap T/2–T variable-spaced feed-forward equalizer is designed to realize reconfigurable 0.5-T, 0.6-T, 0.75-T, and 1-T tap delays, which enables customized eye-opening optimization under different data rates and channel responses. The measurement results show that the energy efficiency of the proposed TX is 0.92 pJ/b with a 0.9-Vppd DC output swing, and the best level separation mismatch ratios are 99.8% and 99.6% at 100-Gb/s and 112-Gb/s, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2664-2675"},"PeriodicalIF":5.2000,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems I: Regular Papers","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10964389/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This study presents a 112-Gb/s four-level pulse-amplitude modulation transmitter implemented in a 28-nm CMOS process. An innovative quasi-voltage-mode driver is proposed, which demonstrates similar bandwidth compared to the current-mode logic driver with an approximately 30% power reduction and provides flexible linearity fine-tuning. The TX architectures with and without the pre-driver stage are optimized to exploit the bandwidth limit further. A three-tap T/2–T variable-spaced feed-forward equalizer is designed to realize reconfigurable 0.5-T, 0.6-T, 0.75-T, and 1-T tap delays, which enables customized eye-opening optimization under different data rates and channel responses. The measurement results show that the energy efficiency of the proposed TX is 0.92 pJ/b with a 0.9-Vppd DC output swing, and the best level separation mismatch ratios are 99.8% and 99.6% at 100-Gb/s and 112-Gb/s, respectively.
期刊介绍:
TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.