{"title":"A 22.5~28.5 -GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS","authors":"Shiping Zheng;Yun Wang;Ziyang Deng;Chen Jiang;Hongtao Xu","doi":"10.1109/TCSII.2025.3563519","DOIUrl":null,"url":null,"abstract":"This brief presents a hybrid phase shifter (PS) that integrates a three-stage switch-type phase shifter (STPS) and a one-stage reflect-type phase shifter (RTPS). The STPS utilizes a flatness-enhanced <inline-formula> <tex-math>$\\pi $ </tex-math></inline-formula>-network topology to reduce phase error and insertion loss (IL) variation by eliminating feedback and resonant capacitors. The RTPS enables continuous phase shifting with a 4-bit capacitor array and varactor. The proposed hybrid PS achieves an IL variation of ±0.7 dB and an RMS phase error of 0.3° to 1.2° in the <inline-formula> <tex-math>$22.5\\sim 28$ </tex-math></inline-formula>.5 GHz range. Compared to existing designs, the hybrid PS offers superior performance in phase accuracy, IL variation, and area efficiency, with a compact area of <inline-formula> <tex-math>$151\\times 342~\\mathrm {\\mu } m^{2}$ </tex-math></inline-formula>, fabricated using standard 40nm CMOS technology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"813-817"},"PeriodicalIF":4.0000,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10974670/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This brief presents a hybrid phase shifter (PS) that integrates a three-stage switch-type phase shifter (STPS) and a one-stage reflect-type phase shifter (RTPS). The STPS utilizes a flatness-enhanced $\pi $ -network topology to reduce phase error and insertion loss (IL) variation by eliminating feedback and resonant capacitors. The RTPS enables continuous phase shifting with a 4-bit capacitor array and varactor. The proposed hybrid PS achieves an IL variation of ±0.7 dB and an RMS phase error of 0.3° to 1.2° in the $22.5\sim 28$ .5 GHz range. Compared to existing designs, the hybrid PS offers superior performance in phase accuracy, IL variation, and area efficiency, with a compact area of $151\times 342~\mathrm {\mu } m^{2}$ , fabricated using standard 40nm CMOS technology.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.