Self-aligned vertical short-channel 2D transistors for CMOS inverter and digital logic circuit

Abstract

Transistors with size-scaling are needed to continue the Moore’s law for large-scale and high-density integrated circuit (IC) applications. However, the previous nanoscale transistors rely on precise lithography technologies, that increases the cost and complexity. This work develops a facile self-aligned etching technique for fabricating the short-channel vertical field-effect transistors (VFETs). The N-MoS₂ VFETs exhibit a low subthreshold swing (SS) of 162 mV/dec, large current density exceeding 70 µA/µm and high on/off ratio up to 2.3 × 10⁸ at bias of 3 V. The P-WSe₂ VFETs also shows an exceptional performance with SS of 82 mV/dec and on/off ratio exceeding 10⁷. By integrating N-MoS₂ and P-WSe₂ transistor, a CMOS inverter is achieved with a high voltage gain of 50 and noise margin of 90.4 %. Consequently, multiple vertical CMOS transistors were further interconnected to construct NAND and NOR logic circuit, demonstrating a basic digital logic application in low-power integrated circuits. The demonstration of 2 × 4 and 2 × 8 transistor arrays in one manufacturing process further proves the potential feasibility of large-scale integration. This work presents a promising pathway for 2D vertical transistor fabrication towards the applications of CMOS inverter and digital integration circuit.