Cache and Near-Data Co-Design for Chiplets

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-04-25 DOI:10.1109/LCA.2025.3564535

Arteen Abrishami;Zhengrong Wang;Tony Nowatzki

引用次数: 0

Abstract

Vendors are increasingly adopting chiplet-based designs to manage cost for large-scale multi-cores. While near-data computing, a paradigm involving offloading computation near where data is located in memory, has been studied in the context of monolithic chip designs – its applications to chiplets remain unexplored. In this letter, we explore how the paradigm extends to chiplets in a system where computation is offloaded to accelerators collocated within the last-level-cache structure. We explore both shared and private last-level-cache designs across a variety of different workloads, both large-scale graph computations and more regular-access workloads, in order to understand how to optimize the cache and topology design for near-data workloads. We find that with a mesh chiplet architecture with shared last-level-cache (LLC), near-data optimization can achieve an 8.70× speedup on graph workloads, providing an even greater benefit than in traditional systems.

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小芯片的缓存和近数据协同设计

供应商越来越多地采用基于芯片的设计来管理大规模多核的成本。虽然在单片芯片设计的背景下研究了近数据计算，一种涉及在内存中数据位置附近卸载计算的范式，但其在小芯片上的应用仍未探索。在这封信中，我们将探讨如何将范式扩展到系统中的小芯片，其中计算被卸载到最后一级缓存结构中并置的加速器。为了了解如何为近数据工作负载优化缓存和拓扑设计，我们探索了跨各种不同工作负载的共享和私有最后一级缓存设计，包括大规模图计算和更常规访问的工作负载。我们发现，使用具有共享最后一级缓存（LLC）的网格芯片架构，近数据优化可以在图形工作负载上实现8.70倍的加速，提供比传统系统更大的好处。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.