L-DTC: Load-based Dynamic Throughput Control for Guaranteed I/O Performance in Virtualized Environments

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-04-10 DOI:10.1109/LCA.2025.3559454

TaeHoon Kim;Jaechun No

引用次数: 0

Abstract

In this letter, we identified an issue where the I/O performance of specific tasks could not be guaranteed during multi-process I/O operations, despite the use of the latest storage technologies in virtualized environments. To address this issue, we propose L-DTC, a novel Load-based Dynamic Throughput Control technique, designed to achieve the guaranteed I/O performance in virtualized environments. Operating at the hypervisor level, L-DTC provides fine-grained throughput control based on I/O queues and ensures the independent I/O performance for each process by allowing users to define maximum and minimum throughput levels for each queue. We conducted an evaluation of L-DTC and confirmed that it successfully guarantees the I/O performance requirements of specific processes in multi-process environments. Furthermore, L-DTC achieved more stable I/O performance compared to existing methods, with improvements in I/O performance of up to 2.1 times, regardless of the I/O scheduler.

查看原文本刊更多论文

L-DTC：虚拟化环境中基于负载的动态吞吐量控制，保证I/O性能

在这封信中，我们发现了一个问题，即尽管在虚拟化环境中使用了最新的存储技术，但在多进程I/O操作期间，无法保证特定任务的I/O性能。为了解决这个问题，我们提出了L-DTC，一种新的基于负载的动态吞吐量控制技术，旨在实现虚拟化环境中有保证的I/O性能。L-DTC在管理程序级别上运行，提供基于I/O队列的细粒度吞吐量控制，并通过允许用户为每个队列定义最大和最小吞吐量级别来确保每个进程的独立I/O性能。我们对L-DTC进行了评估，确认它成功地保证了多进程环境中特定进程的I/O性能要求。此外，与现有方法相比，L-DTC实现了更稳定的I/O性能，与I/O调度器无关，I/O性能的提高高达2.1倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.