A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-04-02 DOI:10.1109/TVLSI.2025.3553400

Jaewon Lee;Seoyoung Jang;Yujin Choi;Donggeon Kim;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim

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引用次数: 0

Abstract

This article presents a 2-lane

$2 \times 2$

multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm²/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e⁻³ to 1.31e⁻⁷ compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist.

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RFSoC平台上基于2通道DAC / adc的2 × 2 MIMO PAM-4 MMSE-DFE有线收发器

本文介绍了一种2通道2 \ × 2$多输入多输出（MIMO） 4级脉冲幅度调制（PAM-4）最小均方误差(MMSE)-决策反馈均衡器（DFE），具有远端串扰（FEXT）消除功能，用于基于数模转换器(DAC) /模数转换器（ADC）的高速串行链路。接收器（RX）数据路径设计有一个15分路MIMO前馈均衡器（FFE）和一个具有最小均方（LMS）的一分路MIMO DFE，能够在保持MMSE设置的同时适应信道变化。28纳米CMOS中的RX数字信号处理器（DSP）位置和路由（PnR）估计以56 gb /s/lane数据速率消耗201 mW/lane，同时占用0.5 mm2/lane硅面积。我们进一步实现了一个实时评估平台，通过在RFSoC上进行快速误码率（BER）测试来验证MIMO PAM-4 MMSE-DFE的功能。测量结果表明，当在Nyquist具有12.4 db插入损耗（IL）和13.2 db IL-串扰比（ICR）的信道上通信时，MIMO MMSE-DFE显着提高了误码率，从2.75e−3到1.31e−7。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.