Simulation study of a 1200V 4H–SiC lateral MOSFETs with Double-RESURFs technology for reducing saturation current

IF 3 Q2 PHYSICS, CONDENSED MATTER

Micro and Nanostructures Pub Date : 2025-05-20 DOI:10.1016/j.micrna.2025.208218

Lijuan Wu, Jiahong He, Zhipeng Shen, Gengbin Zhu, Qiqi Tang, Zongyang Yi, Guanglin Yang, Deqiang Yang

{"title":"Simulation study of a 1200V 4H–SiC lateral MOSFETs with Double-RESURFs technology for reducing saturation current","authors":"Lijuan Wu, Jiahong He, Zhipeng Shen, Gengbin Zhu, Qiqi Tang, Zongyang Yi, Guanglin Yang, Deqiang Yang","doi":"10.1016/j.micrna.2025.208218","DOIUrl":null,"url":null,"abstract":"<div><div>A 1200V 4H–SiC lateral double-diffused MOSFETs (LDMOS) with embedded auto-adjust JFET (AD-JEFT) and double-reduced surface fields technology is proposed. The AD-JEFT, as the conduction path of electrons from N+ source to the P-well channel, is embedded in P+ well. In the on-state, as the device is pressurized, the increase of depletion charge will reduce the effective channel width of AD-JFET. As a result, the potential barrier of the AD-JFET channel will increase rapidly, making it difficult for electrons to transfer and resulting in a reduction of the saturation current. Compared with the common LDMOS (C-LDMOS), the saturation current (<em>I</em><sub>dsat</sub>) of the proposed LDMOS with AD-JEFT (ADJ-LDMOS) is reduced by 53.3 %. Meanwhile, the short circuit capability is improved by 110.5 %. In addition, the top P-type region of ADJ-LDMOS is divided into a higher doped P-top region and a lower doped P-top2 region, which greatly improves the blocking ability. The breakdown voltage was increased by 21.9 % without increasing the specific on-resistance (<em>R</em><sub>on,sp</sub>).</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"205 ","pages":"Article 208218"},"PeriodicalIF":3.0000,"publicationDate":"2025-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325001475","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}

引用次数: 0

Abstract

A 1200V 4H–SiC lateral double-diffused MOSFETs (LDMOS) with embedded auto-adjust JFET (AD-JEFT) and double-reduced surface fields technology is proposed. The AD-JEFT, as the conduction path of electrons from N+ source to the P-well channel, is embedded in P+ well. In the on-state, as the device is pressurized, the increase of depletion charge will reduce the effective channel width of AD-JFET. As a result, the potential barrier of the AD-JFET channel will increase rapidly, making it difficult for electrons to transfer and resulting in a reduction of the saturation current. Compared with the common LDMOS (C-LDMOS), the saturation current (I_dsat) of the proposed LDMOS with AD-JEFT (ADJ-LDMOS) is reduced by 53.3 %. Meanwhile, the short circuit capability is improved by 110.5 %. In addition, the top P-type region of ADJ-LDMOS is divided into a higher doped P-top region and a lower doped P-top2 region, which greatly improves the blocking ability. The breakdown voltage was increased by 21.9 % without increasing the specific on-resistance (R_on,sp).

查看原文本刊更多论文

采用双resurfs技术降低饱和电流的1200V 4H-SiC横向mosfet的仿真研究

提出了一种嵌入自调节JFET （AD-JEFT）和双缩小表面场技术的1200V 4H-SiC横向双扩散mosfet （LDMOS）。AD-JEFT作为电子从N+源到P-阱通道的传导路径，嵌入在P+阱中。在导通状态下，随着器件的加压，耗尽电荷的增加会减小AD-JFET的有效沟道宽度。因此，AD-JFET通道的势垒将迅速增加，使电子难以转移，导致饱和电流降低。与普通LDMOS （C-LDMOS）相比，AD-JEFT （jj -LDMOS）的饱和电流（Idsat）降低了53.3%。同时，电路的短路能力提高了110.5%。此外，ADJ-LDMOS的顶部p型区被划分为高掺杂P-top区和低掺杂P-top2区，大大提高了阻滞能力。在不增加比导通电阻的情况下，击穿电压提高了21.9% （Ron,sp）。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Micro and Nanostructures

CiteScore

6.50

自引率

0.00%

发文量