A low-power, area-efficient digital decimation filter with column-shared counter topology for CMOS image sensor

Abstract

In this paper, a low-power, area-efficient digital decimation filter with column-shared counter for second-order incremental $\Sigma \Delta$ analog-to-digital converter is proposed. A mathematical function transformation is used to reduce the number of transistors by turning the counter into a multicolumn-shared counter, and a 13-bit area-efficient adder design is proposed to further reduce the chip area and power consumption of the digital filter, and the filter operating speed is improved by the modification. The design is implemented with a 130 nm CMOS process. The total area of each digital filter row is $4.5\times 160\mu {\text{m}}^2$, and the number of transistors is 314, which is a 30% reduction compared with the traditional architecture. According to the post-layout simulation, the maximum working frequency is 153 MHz. The total power consumption of the single-column filter without column-shared counter is $2.25\mu \text{W}\sim 4.5\mu \text{W}$ under the clock frequency 50 MHz.