{"title":"Innovative process for the production high-purity zeolites to passivate silicon's surface and bulk to improve electrical parameters","authors":"Wala Medfai , Marouan Khalifa , Rabia Benabderrahmane Zaghouani , Selma Aouida , Hatem Ezzaouia","doi":"10.1016/j.micrna.2025.208212","DOIUrl":null,"url":null,"abstract":"<div><div>Metal impurities in silicon wafers severely degrade solar cell performance, with typical efficiency losses of 15–30 % due to reduced minority carrier lifetimes. While conventional gettering techniques achieve impurity reduction, they require high temperatures (>850 °C) and can introduce wafer damage. This study demonstrates a novel low-temperature (350 °C) gettering approach using Heulandite-Na (HEU-Na) zeolite layers deposited on porous silicon substrates via sol-gel dip-coating. Microwave photoconductance decay (μW-PCD) measurements revealed that the HEU-Na gettering increased minority carrier lifetime from 1.44 μs to 30.68 μs - a 21-fold improvement that surpasses conventional PDG (typically 3-5x enhancement). Surface photovoltage analysis showed diffusion length improvements from 103.27 μm to 324.16 μm, while Hall effect measurements demonstrated a mobility increase from 209.49 to 732.93 cm<sup>2</sup>V<sup>−1</sup>s<sup>−1</sup>. The dual functionality of HEU-Na as both a gettering and passivation layer, combined with its low-temperature processing, offers a cost-effective and industry-scalable approach for improving silicon solar cell efficiency. This method's effectiveness at temperatures below 400 °C makes it particularly valuable for advanced cell architectures where high-temperature processing must be avoided. The findings demonstrate the potential of zeolite-based gettering to revolutionize silicon purification in both photovoltaic and semiconductor industries, potentially reducing manufacturing costs while improving device performance.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"205 ","pages":"Article 208212"},"PeriodicalIF":2.7000,"publicationDate":"2025-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325001414","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
引用次数: 0
Abstract
Metal impurities in silicon wafers severely degrade solar cell performance, with typical efficiency losses of 15–30 % due to reduced minority carrier lifetimes. While conventional gettering techniques achieve impurity reduction, they require high temperatures (>850 °C) and can introduce wafer damage. This study demonstrates a novel low-temperature (350 °C) gettering approach using Heulandite-Na (HEU-Na) zeolite layers deposited on porous silicon substrates via sol-gel dip-coating. Microwave photoconductance decay (μW-PCD) measurements revealed that the HEU-Na gettering increased minority carrier lifetime from 1.44 μs to 30.68 μs - a 21-fold improvement that surpasses conventional PDG (typically 3-5x enhancement). Surface photovoltage analysis showed diffusion length improvements from 103.27 μm to 324.16 μm, while Hall effect measurements demonstrated a mobility increase from 209.49 to 732.93 cm2V−1s−1. The dual functionality of HEU-Na as both a gettering and passivation layer, combined with its low-temperature processing, offers a cost-effective and industry-scalable approach for improving silicon solar cell efficiency. This method's effectiveness at temperatures below 400 °C makes it particularly valuable for advanced cell architectures where high-temperature processing must be avoided. The findings demonstrate the potential of zeolite-based gettering to revolutionize silicon purification in both photovoltaic and semiconductor industries, potentially reducing manufacturing costs while improving device performance.