Addressing interface trap charge sensitivity in tunnel FETs via dual metal gate engineering

Abstract

This study explores a dual-metal-based JL-TFET to address reliability challenges. The work focuses on optimizing gate metal work functions through detailed analysis to enhance device performance. To evaluate the reliability of the proposed JL-DMG-TFET, interface traps near the oxide-semiconductor interface were introduced and analyzed. The reliability assessment was conducted using key parameters critical for low-power applications, with a comparative analysis against conventional devices. Results demonstrate that the JL-DMG-TFET exhibits superior immunity to positive and negative interface traps, making it a promising candidate for energy-efficient and high-frequency linearity applications.