A Practical Design of Single-Slope ADC With Improved Dynamic Range on FPGA

Abstract

The development of field-programmable gate array (FPGA)-based analog-to-digital converters (ADCs) helps to improve system integration, shorten development cycles, and reduce costs. One realization of this is the single-slope ADC, which uses a ramp waveform to intersect the input signal, converting the input voltage into a measurable time interval for digitization. Although existing designs are capable of waveform digitization, there remains considerable potential for further research in terms of design practicality, flexibility, and performance. This article presents an implementation that advances current designs in three aspects. First, by decoupling the ADC sampling clock from the time-to-digital converter (TDC) clock, the ADC’s sampling rate can be reconfigured without the need for firmware resynthesis. Second, the two cross points within a single sampling cycle are combined to convert voltage into pulsewidth for measurement, significantly simplifying the firmware design. Finally, a mapping calibration between time and voltage is applied to improve the ADC linearity while maintaining the widest possible dynamic range. The proposed ADC was implemented on a Xilinx UltraScale+ FPGA for performance evaluation at a 200-MS/s sampling rate and 10-bit resolution. Test results show that the ADC achieves a measurement range of 70–1770 mV with an effective number of bits (ENOB) of 7.2. The differential nonlinearity (DNL) ranges from −0.23 to 0.23 LSB, and the integral nonlinearity (INL) ranges from −1.95 to 1.33 LSB. This ADC design requires no off-chip components, is not susceptible to FPGA placement and routing, and can be implemented as an intellectual property (IP) core, allowing end-users to integrate it into systems without requiring in-depth knowledge of ADC design.