Dual-Rail Asynchronous Quantum Phase-Slip Logic Gates

Abstract

Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly, i.e., the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large-scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation, and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level by eliminating the clocking routes and producing local clock pulses. In this article, design of the dual-rail asynchronous logic gates (and, or, and xor) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit in order to reduce the total number of elements, first, the timed QPS and, or, and xor gates, splitter, confluence buffer, and coincidence junction with a reduced number of elements are designed. Then, these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates is investigated by simulation results. Finally, delay analysis is provided in order to estimate the operation frequency limit of the proposed asynchronous gates.