A New Approach for Mitigating the effects of temperature and ITCs in GAA TFETs with a vertical tunneling design

Abstract

This work proposes an innovative vertical tunneling GAA-VTFET design that enhances analog/AC performance by addressing interface trap effects and temperature variations. Integrating a heavily doped n + source pocket with GaP/Si heterojunction, the device achieves improved BTBT (band-to-band tunneling) efficiency, resulting in higher on-current and a reduced subthreshold slope (SS). The fully source surrounding gate structure enables line tunneling, providing enhanced gate control, while a gate-drain underlap and vertical configuration effectively suppress ambipolar and leakage currents, yielding a high on–off current ratio and compact footprint. DC analysis reveals optimal threshold voltage, high on–off ratio, and low SS, while AC performance metrics, including favourable transconductance, cutoff frequency, and gain-bandwidth product, underscore its suitability for RF and high-performance analog applications.