A New Distributed Attenuator Using DTMOS-With-RB- and Diode-Connected-FET-Based Varistor Units

Abstract

A passive distributed attenuator with high linearity and a wide attenuation range is presented. It consists of four parallel varistor units and three sections of series $\lambda $ /8-transmission line (TL)-based $\lambda $ /6 and 50- $\Omega $ synthetic TLs. Each varistor unit consists of a cascode of DTMOS-with- ${R} _{\text {B}}$ FETs (DFET) M1/M2 in parallel with a cascode of DFET M3 and diode-connected FET M4 and then in series with TL2 for phase compensation of parasitic capacitance. In the low-attenuation state ( ${V} _{\text {ct}} =0$ V), input 1-dB compression point (IP1dB) boosting is attained due to the cascode of M1/M2 and the slowdown of M1 turn-on by the leakage suppression of ${R} _{\text {B}}$ . In the high-attenuation state ( ${V} _{\text {ct}} =2$ V), low gain expansion (smaller than 1 dB for ${P} _{\text {in}}$ up to 20 dBm) is achieved since the varistor unit is equivalent to a parallel resistance (R) of $70~\Omega $ for ${V} _{\text {in}}$ of −4 to 4 V. This is attributed to the cascode of M3/M4 providing a second conduction path at ${V} _{\text {in}}$ that is larger than ${V} _{\text {ct}} - {V}_{\text {th}}$ (1.7 V), where M2 enters the high R saturation region from the low R linear region. The attenuator achieves IP1dB,att ( ${P} _{\text {in}}$ at 1-dB attenuation range reduction) of 20 dBm, one of the best IP1dB,att results ever reported for (Bi)CMOS attenuators. For 4-bit attenuation control (−4 to −19 dB) with 1 dB/step, the attenuator achieves an rms gain error of 0.01–0.5 dB and an rms phase error of 4.5°–5.9° for 37–41 GHz.