Application of Lightweight Target Detection Algorithm Based on YOLOv8 for Police Intelligent Moving Targets

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2025-05-10 DOI:10.1049/cdt2/9984821

Yanjie Zhang, Xiaojun Liu, Yuehan Shi, Zecong Ding, Xiaoming Zhang

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引用次数: 0

Abstract

This study presents an intelligent moving target to replicate mob attacks and other realistic events in police training to match actual fighting needs. The police intelligent moving target must deploy target detection algorithms on the hardware platform, but the traditional you only look once (YOLO)v8 algorithm has a large framework, which will slow recognition due to the hardware platform’s lack of arithmetic power. In this study, GhostNet network architecture replaces YOLOv8^′s backbone network for real-time target identification, improving recognition speed. The bounding box regression issue in target detection uses the scale invariant intersection over union (SIoU) loss function to increase prediction box overlapping and identification accuracy. Finally, BiFormer uses dynamic sparse attention for more flexible computational allocation and content perception. The method’s real-time detection speed is 4.81 frames per second (FPS) faster, [email protected] is 5.38% faster, mean average precision (mAP)@0.5:0.95 is 4.19% faster, and parameter volume is 5.81 M less than the original approach. The approach developed in this work has several applications in real-time target identification and lightweight deployment.

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基于YOLOv8的轻型目标检测算法在警用智能运动目标中的应用

本研究提出了一个智能移动目标来复制暴徒袭击和警察训练中的其他现实事件，以匹配实际战斗需求。警用智能移动目标必须在硬件平台上部署目标检测算法，而传统的you only look once (YOLO)v8算法框架较大，由于硬件平台缺乏算力，会导致识别速度变慢。在本研究中，GhostNet网络架构取代YOLOv8的骨干网进行实时目标识别，提高了识别速度。目标检测中的边界盒回归问题采用SIoU损失函数（scale invariant intersection over union）来提高预测盒重叠和识别精度。最后，BiFormer使用动态稀疏注意实现更灵活的计算分配和内容感知。该方法的实时检测速度比原方法提高了4.81帧/秒（FPS）， [email protected]提高了5.38%，平均精度（mAP）@0.5:0.95提高了4.19%，参数体积比原方法减少了5.81 M。本研究开发的方法在实时目标识别和轻量级部署中具有多种应用。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.