A FinFET based single bit-line feedback cutting Low Power 11T SRAM cell for LPWAN applications

Abstract

This work presents the design of an advanced SRAM bit-cell optimized for LPWAN applications, leveraging FinFET 18 nm technology. The proposed FCLP11T cell is compared with Conventional 6T (CO6T), Transmission gate-based feedback-cutting 9T (TGFC9T), Transmission gate-based read buffers 10T (TGRB10T), Dual PMOS-based read decoupled 10T (DPRD10T), and Dual Stack 10T (DS10T). It demonstrates significant reductions in read and write power dissipation by factors of 1.02$\times$/1.91$\times$/1.75$\times$/1$\times$/1.97$\times$ and 1.54$\times$/1.90$\times$/1.09$\times$/2.29$\times$/1.10$\times$, respectively, compared to CO6T/TGRB10T/TGFC9T/DS10T/DPRD10T SRAM bit-cell design. Additionally, the FCLP11T cell reduces leakage power by 1.29$\times$/1.15$\times$/1.30$\times$/1.17$\times$/ 1.12$\times$ and improves WSNM by 1.39$\times$/1.55$\times$/0.99$\times$/1.38$\times$/1.31$\times$, respectively, compared to CO6T/TGRB10T /TGFC9T/DS10T /DPRD10T SRAM bit-cell design. The RSNM and HSNM are also enhanced by 2.12$\times$/ 1.44$\times$/ 1.55$\times$/1.73$\times$/1.01$\times$ and 1.03$\times$/1.02$\times$/1.03$\times$/1.02$\times$/ 1.01$\times$, respectively, compared to CO6T/TGRB10T /TGFC9T/DS10T/DPRD10T SRAM bit-cell design. . The proposed cell has been tested for Process-Voltage-Temperature variations, highlighting its robust performance and suitability for LPWAN applications.