An Efficient Frequency Compensation Approach for Multi-Stage CMOS Amplifiers

Abstract

Leveraging Miller's concept, a general approach for multi-stage amplifier frequency compensation is proposed. The idea is repeating a Miller pattern on intermediate nodes. In this way Miller capacitor at the output of a differential gain stage, manipulates poles and zeros locations to achieve the desired frequency response. The idea is applied to four and five-stage amplifiers. The linear transfer function (TF) and poles-zeros formulations are calculated for both amplifiers while circuit implementations are simulated using 0.18 μm CMOS technology. According to both theoretical description and simulation results, the proposed frequency compensation appropriately stabilized the amplifier with excellent performance. Obtaining more than 13 MHz for GBW with 83° phase margin while whole the four-stage amplifier consumes less than 320 μW. Ample simulation results are provided to express the reliability and robustness of the proposed approach. In this view, the proposed compensation method besides its design methodology can be used for almost any analog and mix-mode systems such as modulators, sensors, and data converters.