Time Interleaving in the Analogue Circuitry of Oversampled Digital-to-Analogue Converters: Proof of Concept

Abstract

Digital-to-analog converters (DACs) based on sigma-delta modulation are implemented with analog components that have low accuracy requirements. As a result, they have been widely employed in high-frequency transmitter architectures over the past decades. Time interleaving techniques allow parallel structures to operate at reduced speeds, thereby mitigating speed limitations in digital circuits. However, a common approach involves multiplexing the outputs of these parallel structures to reconstruct a single digital signal, which is subsequently converted to an analog voltage using a high-speed, low-resolution DAC. This work investigates the feasibility of employing a parallel array of low-speed DACs instead. To compensate for mismatches in analog paths, a novel dynamic element matching technique is proposed. Experimental results demonstrate that the proposed approach exhibits the characteristics required for high-frequency transmitter applications.