Experimental Validation of ANNA: Analog Neural Network ASIC for Event Positioning in Monolithic Scintillation Detectors

Abstract

machine learning (ML) accelerators represent an attractive area of research, offering the potential to streamline algorithmic complexity and handle massively parallel in-memory computations, with substantial improvements in energy efficiency and speed related to data transmission and processing. Analog computing can further boost ML acceleration due to its superior computational density compared to digital platforms and its ability to deal with analog data acquired from sensors. The analog approach to edge computing can be beneficial for signal processing in long-axial field-of-view (LA-FOV) scintillation detectors used in nuclear medical tomographic imaging (PET and SPECT). In such scenarios, the deployment of analog computations in close proximity to the sensors would significantly diminish the volume of data that must be digitized and transmitted, and ML reconstruction algorithms, such as neural networks (NNs), could enhance the image reconstruction process. We present an ASIC fabricated in 0.35- $\mathrm { {\mu }\text {m}}$ CMOS technology implementing an analog NN featuring 64 inputs, two hidden layers of 20 neurons each, and two outputs. It is intended for use in the reconstruction of the 2-D position of interaction of gamma photons inside a monolithic scintillator crystal readout by a matrix of silicon photomultipliers (SiPMs) for PET/SPECT applications. This chip can interact directly with analog signals originating from the photosensors, and is able to provide the predicted interaction coordinates of the gamma-ray at its output. The vector-matrix multiplications for inference are executed in the charge domain using programmable switched capacitors (SC) organized in crossbar arrays. Experimental measurements of this first proof-of-concept prototype ASIC are reported, demonstrating the correct functionality of the NN circuit. With an energy efficiency of $50~{\mathrm {GOPS/W}}$ and power consumption of $17~{\mathrm {mW}}$ per inference, the achieved results are promising for the integration of the ASIC with the photodetector front-end for in situ analog computing.