A 10-Bit 500-MS/s Pipelined SAR ADC With Feedback Factor Compensation in 6-nm FinFET

Abstract

This brief introduces an energy-efficient 10-bit 500-MS/s pipelined SAR ADC that uses feedback factor compensation in 6-nm FinFET technology. The design challenges of residue amplifier in FinFET technology are adequately addressed by incorporating feedback factor compensation. This includes a dynamic negative capacitance circuit at the virtual ground that compensates for the feedback factor and relaxes the requirements of the residue amplifier. This enables the use of an inverter-based residue amplifier that can achieve a high-speed operation of 500-MS/s at a low supply voltage of 0.9 V. The prototype ADC is fabricated in a 6-nm FinFET and occupies 0.014 $\text {mm}^{{2}}$ . With a Nyquist input signal, it achieves an SNR of 54.2 dB and an SNDR of 53.6 dB, while consuming 2.7 mW from a 0.9 V supply voltage. This brief achieves a competitive Walden figure of merit (FoM) of 13.8 fJ/conv.-step.