ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection

Abstract

In-situ timing monitoring technology is widely used in adaptive voltage scaling (AVS) system to provide real-time timing information, enabling the elimination of timing margins preserved for PVT variations. However, the increased number of monitors and the short-path issue result in significant overhead. In this brief, a low-cost in-situ mechanism, intersection timing prediction and path activation detection (ITP-PAD), is proposed. It performs timing monitoring and path activation detection at the intersection of critical paths. Additionally, critical path replica (CPR) is introduced to support the ITP-PAD. A low-overhead 12-transistor (12-T) transition detector (TD) is designed to detect timing information and path activation, which operates stably at a sub-threshold voltage of 0.26 V. Furthermore, a method for selecting the minimum intersection points of critical paths has been proposed to reduce the number of insertion points.Implemented on an ARM Cortex-M0 microcontroller in 22nm technology, this approach reduces the insertion rate from 13.4% to 1.1%, with a total area overhead of only 1.3%. Measurements show that the chip’s power consumption is reduced by 36.9% to 51.1% over a voltage range of 0.42 V to 0.8 V.