Robust and Reliable Energy-Efficient Level Shifter

Abstract

In this brief, we propose an energy-efficient level shifter (LS) for converting a wide range of supply voltages for digital integrated circuit applications. The proposed novel circuit is a two-stage LS comprising of current mirror (CM) based circuit followed by the split inverter. A feedback mechanism, current-limiter PMOS, and pass transistor are used to resolve the current contention, static power dissipation, and improved minimum conversion time. The proposed LS shows a reduced impact of variability across various PVT corners, making it a viable solution for low-voltage digital systems. The proposed LS shows a propagation delay of 3.01 ns (0.67 ns), an energy per transition of 1.84 fJ (0.595 fJ) for converting 0.3 V (0.2 V) to 1.2 V (1 V) in CMOS 65 nm (FDSOI 28 nm) process, and a lower energy-delay product (EDP) compared to current state-of-the-art designs. With static power dissipation of 280 pW at 0.3 V input, it also features an average minimum convertible input level ( $\rm V_{DDL}$ ) of 100 mV at a 1-MHz (20-MHz) frequency. Simulations were performed in a commercial CMOS 65 nm and FDSOI 28 nm processes with Cadence VIRTUOSO and Synopsys HSPICE environments.